A low dropout regulator (LDO) is a DC linear voltage regulator which can operate with a very small input-output differential voltage. In conventional low dropout voltage regulators i.e. LDOs, it is necessary to couple an off-chip capacitor at the output of the LDO which generates a low frequency dominant pole at the regulated output node in order to obtain stability. The low frequency dominant pole at the output node provides stability while maintaining a good transient response, however the off-chip capacitor increases bill of material and consumes significant board area.
Current trends in technology demand miniaturization of electronic devices and thus the off-chip capacitor in a conventional LDO needs to be eliminated. The dominant pole may still be implemented on the regulated output node by replacing the off-chip capacitor by an on-chip one, however such a dominant pole varies widely with the load current due to small value of on-chip capacitance available thus rendering it ineffective for certain loads. Alternatively, when the dominant pole is realized on an internal node the slew rate is degraded resulting in a slower transient response.
FIG. 1 illustrates the ripple response of a conventional LDO for a load that generates a train of spike currents such as a clock tree network. FIG. 1(a) shows the block diagram of the conventional LDO while FIG. 1(b) shows the train of spike currents and corresponding ripple in the output voltage at each clock edge. The maximum peak current (IP) occurs at the rising edge of the clock when inverters at the final stage of the clock tree charge their load capacitances. On the falling edge of the clock, the peak current drawn from the supply is reduced by a value equivalent to the stage ratio in the clock tree (IP/N). This is due to the reduction of the number of clock tree inverters charging their load capacitances on this edge of the clock by a value equivalent to the stage ratio.
FIG. 2 illustrates a conventional technique to evaluate the transient response of the low dropout voltage regulator (LDO) for a step change in the load current. The response time (TR) is defined as the minimum time required by the LDO to attain a required output current after the application of the load. Simulation of LDO's response with load transient stimuli both in the form of a train of current spikes and step change in the load current enables the evaluation of the total transient variation on the regulated output voltage of LDO. The ripple response of LDO with a train of spike current is crucial to estimate jitter in the clock when the clock tree is optimized for minimum clock skew. On the other hand, a step change, which occurs when the clock signal suddenly starts (or stops) to propagate down the clock tree, alters the average consumption from low (or high) to a high (or low) value during the propagation delay period in the clock tree.